Available for engineering opportunities

HELLO, WORLD! I'M

Aarush Arya

Microelectronic systems engineer

I build fast, dependable systems where software meets silicon, from RISC-V firmware and FPGA datapaths to custom DSP pipelines and VLSI.

View buildsDownload CV
PLAYER: AARUSHLVL: MSc

HOVER / FOCUS FOR ALT POSE

SYS.READY

RISC-V // FPGA // EMBEDDED C // DSP // VLSI

01 // Experience

Where I have shipped

Hands-on work across microelectronics, robotics, firmware, PCB design, and engineering software.

Jun 2026 - Aug 2026

Microelectronics Engineer Intern

Apitronix Semiconductor Ltd. // York, UK

  • Contributed to pre-silicon development of a safety-critical dual-core RISC-V processor based on RV32I and Hazard3.
  • Brought up the Hazard3 soft-core SoC on a Lattice ECP5 FPGA, integrated CTIO peripherals, and established JTAG program-and-debug through OpenOCD and GDB.
  • Built a discrete single-slope ADC and wrote bare-metal Embedded C firmware to capture timing and linearise its response with calibrated lookup tables.
  • Designed a two-channel CANPico physical-layer daughterboard in KiCad using dual TCAN6062V-Q1 transceivers.
  • Engineered a custom four-layer adapter PCB in KiCad for the AtomHive CoB, integrating a high-density 70-pin mezzanine connector, an Arm-compliant JTAG interface, and custom clock generation for hardware prototyping.
RISC-VHazard3Lattice ECP5Embedded COpenOCDGDBKiCad

Jun 2024 - Sep 2024

Software Intern

National Manufacturing Institute Scotland // Glasgow, UK

  • Developed a custom Behaviour Tree GUI in Python and PyQt to simplify collaborative-robot task management in manufacturing environments.
  • Engineered synchronous and asynchronous execution logic for concurrent tasks and added scalable SVG visual support.
  • Worked across software, hardware, and robotics teams using Git-based code review and real-world system feedback.
PythonPyQtBehaviour TreesAsync systemsSVGGit

Jun 2023 - Aug 2023

IT Software Intern

Forcepoint Ltd. // India

  • Developed proficiency in Go and MySQL while managing application data and maintaining database integrity.
  • Used GORM object-relational mapping to build a fully functional banking application.
  • Contributed within a dynamic product team and gained direct exposure to the cybersecurity industry.
  • Built a command-line interface with GORM for clear and efficient database operations.
GoMySQLGORMCLICybersecurity

02 // Selected builds

Technical quests

Measured engineering work across FPGA acceleration, bare-metal DSP, processor design, and on-device TinyML.

BUILD_01Feb 2026 - May 2026

NLOS SDR Bare-Metal Transceiver

Recovering signal where line-of-sight ends.

A bare-metal communication stack for the Altera DE1-SoC, combining the Cyclone V FPGA and dual-core Arm Cortex-A9 HPS with custom FIR and FFT processing chains.

9.3x
DSP speedup
72 ms
NEON runtime
8,192
I/Q samples
Embedded CNEON SIMDFFTFIRCyclone VArm Cortex-A9
BUILD_02Feb 2026 - Apr 2026

Hardware-Accelerated Risk Filter

Deterministic protection before a trade leaves the wire.

An ultra-low-latency pre-trade engine on the Cyclone V FPGA that intercepts fat-finger errors and compliance breaches through a custom stateful Verilog datapath.

20 ns
Validation latency
10
Parallel rules
1 clk
Deterministic path
VerilogFPGACyclone VRisk controlsLow latency
BUILD_03Jan 2025 - Apr 2025

Custom Processor + VGA System

A processor, memory, and display pipeline built from logic.

A three-phase custom processor implementation on FPGA, including a frame buffer, dual-port video memory, precise VGA timing, raster scanning, and an IR subsystem.

3
Build phases
VGA
Custom display
RTL
System design
VerilogFPGAVGADual-port RAMIRDigital design
BUILD_04May 2026 - Aug 2026

Smart Table Tennis Training System

A racket that classifies each stroke on-device.

An untethered smart racket sampling a six-axis BMI270 IMU at 100 Hz. Peak-centred one-second windows become 78 spectral features for a five-class INT8 neural network running on an Arm Cortex-M4F, evaluated on a separately recorded and physically remounted test session.

90.91%
Held-out accuracy
22 ms
DSP + inference
99.07%
BLE packet delivery
TinyMLINT8BMI270Cortex-M4FBluetooth LEEdge ImpulseEmbedded C
Read MSc dissertation
View racket architecture
Internal electronics of the smart table tennis racket, including the microcontroller, battery, charger, and boost converter

Racket internals: Arduino Nano 33 BLE Sense Rev2, 400 mAh LiPo, TP4056 charger, and 5 V boost hardware inside the printed handle.

Explore my GitHub

03 // Hardware & tooling

My loadout

A practical toolkit spanning bare-metal code, digital logic, system modelling, board design, and developer tooling.

0x01

CORE LANGUAGES

  • C
  • C++
  • Python
  • Verilog
  • Go
  • Java
  • SQL
  • Bash
0x02

SILICON + SYSTEMS

  • FPGA
  • VLSI
  • RISC-V RV32I
  • Arm Cortex
  • Cyclone V
  • Lattice ECP5
  • CAN
  • DSP
  • RTOS
0x03

TOOLS + PLATFORMS

  • Quartus Prime
  • MATLAB
  • KiCad
  • LTspice
  • GDB
  • OpenOCD
  • STM32CubeIDE
  • Git
0x04

SOFTWARE STACK

  • PyQt
  • MySQL
  • Neo4j
  • Cypher
  • Haskell
  • VS Code
  • GitHub
  • SVG

04 // Education

Academia

Research-led degree work spanning on-device intelligence and database performance.

Sep 2025 - Present

MSc (Eng) Embedded Systems Engineering

University of Leeds

Dissertation built an untethered smart table tennis racket that runs a five-class INT8 TinyML pipeline on a Cortex-M4F, reaching 90.91% accuracy on an independently recorded test session.

Sep 2021 - Jul 2025

B(Hons) Electronics & Computer Science

University of Edinburgh

Dissertation compared recursive queries across MySQL and Neo4j, supported by a custom recursive-descent parser in Python.

READY PLAYER TWO?

Let's build something close to the metal.

I'm open to microelectronic systems, FPGA, digital design, and low-level software opportunities.

Start a conversation

contact.sh

$ ./find-aarush --online

Emailaarusharya88@gmail.comGitHubgithub.com/aarucheLinkedInConnect on LinkedIn

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